Advances in computer processor speeds increasingly highlight a growing gap between the relatively high speed of the computer processors and the relatively low speed of computer memory systems. If a computer processor is constantly waiting for data from the memory system, the speed of the processor cannot always be utilized.
One way to increase the speed of a computer memory system is to improve the memory hierarchy design of the computer memory system. Computer memory systems typically include different levels of memory, including fast cache memory, slower main memory, and even slower disk memory. Improved designs of cache memory increase the likelihood of a cache memory “hit”, which avoids the time penalty of having to retrieve data from main memory.
One improved type of cache memory is sector cache. With sector cache, a cache “line” is divided into sub-sectors. One example of sector cache is found on the Pentium 4 processor from Intel Corp. The Pentium 4 processor includes an L2 cache which has a 128-byte long cache line that is divided into two 64-byte sub-sectors.
With sector cache, a cache line miss results in all sub-sectors of the cache line being marked as “invalid” using an invalid bit. However, only a single sub-sector is read on a miss. Therefore, the remaining sub-sectors of the line continue to have invalid or unusable data that takes up space in the cache memory.
Based on the foregoing, there is a need for an improved cache memory system having sub-sectors.